The wiring used in semiconductor packages (hereinafter referred to as LSI packages) is conventionally formed by using a photolithographic method. This wiring structure and wiring forming method are described in detail with reference to FIGS. 1A to 1I.
LSI chip electrode pad 2 connected to internal circuits is provided on a main surface of LSI chip 1. First insulating resin 3 is formed on the main surface, leaving a portion corresponding to chip electrode 2 exposed. On first insulating resin 3 of the substrate including LSI chip 1, copper film 15, which is a wiring layer base, is formed by sputtering or the like, as shown in FIG. 1A. Next, photosensitive resin 16 to be used as an etching resist is applied by spin coating or the like (FIG. 1B). Thereafter, as shown in FIG. 1C, photomask 17 is used to expose and develop a portion for forming a pattern. As a result, photosensitive resin 16 is divided into unexposed portion 16a and exposed portion 16b (FIG. 1D).
Next, the resin of unexposed portion 16a, which is the resin outside developed portion 16c, is removed to form an etching resist (FIG. 1E). By etching away the copper outside a wiring portion forms, copper wiring 18 is formed as the wiring pattern (FIG. 1F). Thereafter, the etching resist is removed (FIG. 1G).
Next, to protect copper wiring 18, second insulating resin 7 is formed as a solder resist on portions other than external electrode pads (FIG. 1H). Further, to form a barrier layer to suppress diffusion of copper into solder that is to be provided on the external electrode pads, plating layer 6 made either of Ni, Ni/Au, Ni/Pd/Au or the like is formed (FIG. 1I). Thus the manufacture of the wiring used in the LSI package is completed.
A further method, which also makes use of photolithography as well as the above-described method, is disclosed in Japanese Patent Laid-Open No. 2003-174118.